1. Field of the Invention
The present invention relates to a semiconductor memory device capable of storing, e.g., data of two values or more in one memory cell.
2. Description of the Related Art
For example, in a NAND type flash memory, a plurality of memory cells, which are arranged in a row direction, are connected to latch circuits via bit lines, respectively. Each latch circuit holds data at a time of data write and data read. Batch data write or read is executed in the plural memory cells arranged in the row direction (see, e.g., Jpn. Pat. Appln. KOKAI Publication No. 2004-192789).
In an erase operation, the threshold voltage of the memory cell is made negative. By a write operation, electrons are injected in the floating gate of the memory cell, thereby making the threshold voltage positive. However, since the memory cells are connected in series in the NAND type flash memory, it is necessary that non-selected cells, other than a selected cell, be turned on when data of the selected cell is read to the bit line in a read operation. Thus, a voltage (Vread), which is higher than a maximum threshold voltage set in the memory cell, is applied to the control gates of the non-selected cells.
On the other hand, in the write operation, the threshold voltage set in the memory cell cannot exceed Vread in consideration of the read operation. It is thus necessary to execute, in the write sequence, a control to prevent the threshold voltage of the memory cell from exceeding Vread, by repeatedly executing program and program verify for each bit.
In the meantime, in order to increase memory capacity, a multi-value memory which stores data of two bits or more in one memory cell has been developed. For example, in order to store two bits in one memory cell, it is necessary to set four threshold distributions. Thus, in the case of the multi-value memory, it is necessary to make each threshold distribution narrower than in the case of a memory which stores one bit in one cell. As a result, there is a problem that the write speed decreases.
It is thought that high-speed write is enabled by setting a threshold voltage also on the negative side and increasing the width of each threshold distribution. As a method of setting the threshold voltage on the negative side, it has been proposed to apply a bias voltage to the source of the cell and the well at the time of read and verify read, thereby making the potentials of the source and well higher than the potential of the word line. Thus, it becomes possible to apparently realize an equivalent case in which a negative voltage is applied to the word line, and it becomes possible to read a negative threshold voltage. In the case of this proposed method, the source and well, on the one hand, and the non-selected bit line, on the other hand, are short-circuited so as to prevent a large current from flowing to a power supply circuit, which generates the bias voltage, from many bit lines of, 16K to 32K. In the read operation, a potential is first applied to a selected bit line of two bit lines. At this time, a charge (+Q) is accumulated in the selected bit line, and a charge (−Q) is accumulated in the non-selected bit line. If the cell is turned on, the charge that is accumulated in the selected bit line flows to the source. However, since the source and the well, and the non-selected bit line are short-circuited, the charge of the selected bit line flows to the non-selected bit line, and the charge of the selected bit line is neutralized with the charge (−Q) accumulated in the non-selected bit line and is erased. Accordingly, source noise can be suppressed and high-speed read is enabled. Moreover, since little current flows into the power supply circuit that supplies the bias voltage to the source and well and the non-selected bit line, the power supply circuit stably operates and the threshold voltage on the negative voltage side can be surely read.
In this case, however, since the charge (−Q) accumulated in the non-selected bit line needs to be let to flow to the source line, simultaneous read can be executed from only half the plural cells arranged in the row direction. In the case where only half the plural cells arranged in the row direction can be selected, a write operation is executed in units of half the cells. Consequently, the non-selected cell suffers program disturb. In order to increase the write speed, it is desirable to simultaneously write data in all the plural cells arranged in the row direction. By connecting data storage circuits to all the bit lines, it becomes possible to simultaneously write data in all the cells arranged in the row direction.
However, in the data read operation, as described above, it is necessary to use one of neighboring two bit lines and thereby to erase the charge of the other bit line. As a result, data read can be executed only in units of half the plural cells arranged in the row direction, and read cannot be executed from all the cells at the same time. This data read is not limited to ordinary read, but is similarly applicable to verify read for verifying write data. In particular, in the case of multi-value memories which store 4-value, 8-value and 16-value data, the number of times of verify read increases in order to verify write data. Because of the write time, the time that is needed for the write verify increases. As has been described above, in the case where the bias voltage is applied to the source line at the time of data read, there is the problem that simultaneous data read cannot be executed stably and at high speed from all cells arranged in the row direction, with noise being suppressed. Therefore, there is a demand for the advent of a semiconductor memory device which can simultaneously read data from all cells in the row direction stably and at high speed.